The product is a package substrate that is used for the core semiconductors of mobile devices and PCs. It transmits electric signals between semiconductors and the main board. Compared with general substrates, as this substrate is a high-density circuit substrate containing more microcircuits, the assembly defects and incurred costs in directly bonding expensive semiconductors to the substrate can be reduced.
FCCSP (Flip Chip-Chip Scale Package)
This is called Flip Chip Chip Scale Package (FCCSP) as semiconductor chips are upturned and connected to a board through a bump rather than wire bonding. It is mainly used for the application processor (AP) chips of mobile IT devices.
Features of Products (Technology)
Different from wire bonding, input and output are formed on the semiconductor (chip) through an area array, and then the chip is flipped and connected to the PCB
Compared to WBCSP using Gold Wire, the process using Flip Chip can be applied to high-density semiconductors because the route of electrical signals is shorter, and larger input and output can be accommodated.
For the first time in the world, BSP (Blue Stencil Printing) method is applied to mass production
- Available for fine bump pitch
- Good for small bump risk
- High productivity of bump processing
- Competitive price by high productivity & high yield
EPS (Embedded Passive Substrate) is a substrate that has an internally embedded semiconductor passive component.
The decoupling capacitor is normally used to stabilize the power supply voltage level. When embedded inside a substrate, power ground/network inductance can be reduced.
Embedded Trace Substrate (ETS) is a circuit board whose circuit pattern is in the insulating material.
ETS is coreless. Without the increase in costs, fine circuits can be formed. (L/S 15/15 @MSAP) These patterns allow the layer down design. (4 L → 3 L)
As the etching process is not affected by the pattern width, the circuit width can be precisely controlled.
Line-up by Specification
- Mass Production
- Sample Available
|Mass Production||Sample Available|
|Routing Density||Build-up L/S||Mass Production15 / 15||Sample Available12 / 12|
|BVH / Pad Registration||Mass Production65 / 110 ± 22.5||Sample Available65 / 110 ± 17.5|
|SRO Dia. SR Registration||Mass Production70 ± 12.5||Sample Available60 ± 10|
|FC Bump Pitch (Peripheral)||Mass Production40||Sample Available30|
|FC Bump Pitch (Area)||Mass Production148||Sample Available125|
|Low Z-Height||Core / PPG||Mass Production60 / 25||Sample Available40 / 25|
|Cu / SR Thickness||Mass Production15 / 12||Sample Available12 / 10|
|Certification Standards||Certification No||Issue Date||Expiry Date||Certification|
|Thesis_Molecular dynamics study of thermal expansion of polymer||2016-08-18||Admin||Request|
|Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish||2016-08-18||Admin||Request|
|[Patent]US 8039761 (2011.10.18) Printed circuit board with solder bump on solder pad and flow preventing dam||2016-08-18||Admin||Request|