The product is a package substrate that is used for the core semiconductors of mobile devices and PCs. It transmits electric signals between semiconductors and the main board. Compared with general substrates, as this substrate is a high-density circuit substrate containing more microcircuits, the assembly defects and incurred costs in directly bonding expensive semiconductors to the substrate can be reduced.
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FCCSP (Flip Chip-Chip Scale Package)
This is called Flip Chip Chip Scale Package (FCCSP) as semiconductor chips are upturned and connected to a board through a bump rather than wire bonding. It is mainly used for the application processor (AP) chips of mobile IT devices.
Compared to WBCSP using Gold Wire, the process using Flip Chip can be applied to high-density semiconductors because the route of electrical signals is shorter, and larger input and output can be accommodated.
Different from wire bonding, input and output are formed on the semiconductor (chip) through an area array, and then the chip is flipped and connected to the PCB
BSP(Blue Stencil Printing)
For the first time in the world, BSP method is applied to mass production
- Available for fine bump pitch
- Good for small bump risk
- High productivity of bump processing
- Competitive price by high productivity & high yield
EPS(Embedded Passive Substrate)
EPS is a substrate that has an internally embedded semiconductor passive component.
The decoupling capacitor is normally used to stabilize the power supply voltage level. When embedded inside a substrate, power ground/network inductance can be reduced.
ETS(Embedded Trace Substrate)
ETS is a circuit board whose circuit pattern is in the insulating material.
ETS has a coreless structure, which allows for the implementation of microcircuits without the need for additional cost. Layer Down is performed much easier (4L → 3L).
As the etching process is not affected by the pattern width, the circuit width can be precisely controlled.
Line-up by Specification
- Mass Production
- Sample Available
|Mass Production||Sample Available|
|Routing Density||Build-up L/S||Mass Production9 / 12||Sample Available10 / 10|
|BVH / Pad Registration||Mass Production60 / 90||Sample Available60 / 85|
|SRO Dia. SR Registration||Mass Production64 ± 15||Sample Available55 ± 10|
|FC Bump Pitch (Peripheral)||Mass Production35||Sample Available30|
|FC Bump Pitch (Area)||Mass Production130||Sample Available125|
|Low Z-Height||Core / PPG||Mass Production60 / 25||Sample Available40 / 25|
|Cu / SR Thickness||Mass Production10 ± 5||Sample Available8 ± 4|
|Certification Standards||Certification No||Issue Date||Expiry Date||Certification|
|Thesis_Molecular dynamics study of thermal expansion of polymer||2016-08-18||Admin||Request|
|Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish||2016-08-18||Admin||Request|
|[Patent]US 8039761 (2011.10.18) Printed circuit board with solder bump on solder pad and flow preventing dam||2016-08-18||Admin||Request|