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Package Substrate

The product is a package substrate that is used for the core semiconductors of mobile devices and PCs. It transmits electric signals between semiconductors and the main board. Compared with general substrates, as this substrate is a high-density circuit substrate containing more microcircuits, the assembly defects and incurred costs in directly bonding expensive semiconductors to the substrate can be reduced.

SiP(System in Package)

This product is developed by realizing complex functions into one system by mounting multiple ICs and passive components in a package.

  • SiP(System in Package) 제품 01
  • SiP(System in Package) 제품 02
  • SiP(System in Package) 제품 03
  • SiP(System in Package) 제품 04

General Features

  • Smaller Package size compared to individually-packaged Ics
  • Heat dissipation characteristics

Application

  • PA(Power Amplifier), PAD(Power Amplifier Duplexer)
  • FEMID (Front-end module with integrated duplexer)
  • SAW Filter, BAW Filter
  • Various RF parts like diversity FEM and switch

Why Samsung

Miniaturization and thin substrates are available.

Miniaturization

Can realize small packages as multiple ICs and passive components are integrated into one module.

SIP Features

Thin substrate

Can realize 0.2mm thin substrate (based on a 6-layer substrate) by securing the driving capability of ultrathin sheets.

Coreless RF-SiP Substrate

It can realize thin substrates by applying the coreless method.

Coreless RF SiP

Signal characteristics can be enhanced by controlling Electromagnetic Interference (EMI) and the parasitic inductance by lowering the insulation thickness through the application of the coreless method.

Thin Ni ENEPIG

RF performance is possible based on the Ni thickness.

Bonding Pad의 Ni 두께를 기존 5~6.5㎛에서 0.1㎛로 감소하여 RF 특성을 개선하였습니다.

1) ENIG : Electroless Nickel Immersion Gold

2) ENEPIG : Electroless Nickel Electroless Palladium Immersion Gold

Selective ENEPIG

Selective ENEPIG allows the treatment of different surface types on the same board. (ENEPIG + OSP)

1) OSP : Organic Solderability Preservative

Line-Up

Line up by Specification

  • Mass Production
  • Sample Available
SIP(SYSTEM IN PACKAGE) Line-Up
Layer Structure Cored Mass Production4L / 6L / 8L Sample Available4L / 6L / 8L
Coreless Mass Production5L / 7L Sample Available6L / 8L / 9L
Line / Space Mass Production25 / 25 ㎛ Sample Available20 / 30 ㎛
Bump pitch Mass Production150 ㎛ Sample Available130 ㎛
CuT Mass Production15 ㎛ Sample Available15 ㎛
Surface Finish Mass ProductionDirect Au, Thin ENEPIG Selective ENEPIG Sample AvailableDirect Au, Thin ENEPIG Selective ENEPIG

Product Series

  • TEV (Thermal Enhanced Via)
  • SSV (Solid Stack Via)
  • Flip-Chip SiP
  • Coreless

Certificate

Certificate Certification Standards, Certification No, Issue Date, Expiry Date, Certification 등이 있습니다.
Certification Standards Certification No Issue Date Expiry Date Certification
ISO 14001 KE191620 2019-06-10 2022-06-24 Download
ISO 14001 EMS_646840 2018-09-06 2021-09-05 Download
ISO 45001 KS19017 2019-06-10 2022-06-09 Download
ISO 50001 BK60004 2016-06-28 2019-06-27 Download

Technical Article

Technical Article 문서의 제목, 날짜, 등록자, 신청하기 등을 제공합니다.

Patent

[Patent]Patent No. : US 8729395 (2014.05.20) Wire bonding joint structure of joint pad, and method for preparing the same 2016-08-17 Admin Request