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Package Substrate

高密度电路基板

首页产品基板Package Substrate

是移动设备和PC用半导体Package基板，它扮演半导体和主板间传送电信号以及保护昂贵半导体不收外部压力影响的角色。形成比普通电路板更精细的超高密度电路，可减少将昂贵的半导体直接贴装在主板时发生的组装不良率及成本。

FCCSP(Flip Chip Chip Scale Package)

半导体不是通过引线键合方式与基板连接，而是在倒装的状态下通过凸点与基板互连，因此而被称为“FCCSP”(Flip Chip Chip Scale Package)。主要用于移动IT设备的AP（Application Processor）半导体上。而且与采用Gold Wire的WBCSP相比，FCCSP的电信号路径更短，生成更多Input/Output，可适用于高密度半导体。

应用
移动应用程序处理器、Baseband等
半导体 Chip -> Bumping(Solder) -> Flip -> Packaging(PCB)

主要核心技术

1. Bumping 结构图
Bumping Structure image
2. μBall Bump 工艺
μBall Bump Method image
[Conventional 工艺]
Solder Paste -> Squeegee -> Metal mask
[Micro Ball 工艺]
MetalMask -> SolderBall
  • · Available for Fine Bump Pitch
  • · Good for Small Bump Risk
  • · Good Quality for Bump Characteristics

基板种类

1. EPS(Embedded Passive Substrate) & EDS(Embedded Die Substrate)

EPS/EDS是在基板内安装半导体被动元件和IC等，能够量产的基板。
Decoupling Capacitor一般用来稳定Power Supply Voltage Level，如果把IC安装在基板内，
就可以减小封装大小和厚度。

EPS, EDS
2. ETS(Embedded Trace Substrate)

ETS 是线路图形被埋入绝缘基材里面的线路板。基板采用Coreless结构，无需增加Cost，就可形成微细线路，易于进行“Layer Down”设计（4L → 3L）。
而且蚀刻工艺不会影响到图形宽度，因此，可对线路宽度进行精密控制。

[2Layer Buried Trace], [3Layer Buried Trace], [4Layer Buried Trace]

Lineup

Lineup by Specification
Mass Production Sample Available
Lineup by Specification Routing Density, Build-Up Line Width / Space etc.
Routing Density Build-Up Line Width / Space 8 / 10um 7 / 9um
BVH / Pad Registration 50 / 80um 45 / 75um
SRO Diameter SR Registration 55 ± 8um 50 ± 8um
FC Bump Pitch (Peripheral) 35um 30um
FC Bump Pitch (Area) 125um 125um
Low Z-Height Core / PPG Thickness 40 / 18um 35 / 15um
SR Thickness 8 ± 3um 7 ± 2um

WBCSP(Wire Bonding Chip Scale Package)

通过Gold Wire连接半导体芯片和封装基板，半导体 Chip 大小超过基板面积 80% 的产品一般被称为WBCSP。利用Gold Wire连接Chip和 PCB，可以实现多功能封装，主要用于内存 Chip。尤其可以生产厚度不到0.13mm的 UTCSP(Ultra Thin CSP) 产品，Chip to PCB Connection十分自由，能够实现 Multi Chip Packaging，实现比相同厚度的 Package 更高的性能。

应用
智能手机用内存条
Computer
  • 1. Mold
  • 2. Tape Substrate
  • 3. Gold Wire
  • 4. Solder Ball
  • 5. Copper Trace
  • [Gold Wire连接图]

Lineup

Lineup by Specification
General WBCSP Road Map of HVM / Sample Product Mass Production Sample Available
Lineup by Specification Routing Density, Bond Finger Pitch etc.
Routing Density Bond Finger Pitch 65P (37 / 15, Ni 2) 60P (32 / 15, Ni 2)
Line Width / Space 50 Pitch 40 Pitch
SRO Diameter Tolerance ± 15um ± 10um
Ball SR Registration
(After Compensation)		 ± 17.5um ± 16um
Low Z-Height Core/PPG
Thickness		 2Layer 80um 80um
3Layer 80um 80um
4Layer 120um 120um
Lineup by Structure
Mass Production Sample Available
Lineup by Structure Core, Layer, Pattern etc.
Core Layer Count Pattern Structure
Cored 2Layer Normal
Cored 4Layer Normal
Coreless 3Layer Normal
Coreless 4Layer Normal

SiP(System in Package)

Package 内贴装有多个 IC和 Passive Component，通过一个System实现综合功能的产品。而且用于 PA(Power Amplifier)等产品中，具有散热特性。
产品系列有 Flip-Chip SiP和 Coreless。

应用
PA(Power Amplifier), PAMID (Power Amplifier Module with Integrated Duplexer), FEMID(Front-End Module with Integrated Duplexer),
SAW Filter, BAW Filter, Diversity FEM, Switch 等各种 RF元件

特点

1. 小型化

将多个 IC 和被动元件综合在一个 Module中，可实现 Package 小型化。

[SiP 构成图]
  • 1. Sip
  • 2. Die 1
  • 3. Die 2
  • 4. Die 3
2. 实现厚度小的薄板

确保超薄板驱动性，可实现 0.2mm 厚度基板（6层标准）。

[ 0.2T 6L RF-SiP ](200um), [ 0.27T 8L RF-SiP ](270um), [ 10L ~, 5G 天线模块 ]

主要核心技术

1. Coreless RF-SiP

通过Coreless 工艺缩小绝缘厚度，能够控制 EMI(Electro Magnetic Interference) 和 Parasitic Inductance，提升信号特性可以此为基础实现 Thin Substrate。

Cored 基板, Coreless 基板 *可实现Thin Substrate
2. ENEPIG 表面处理

ENEPIG 表面处理技术具有如下特性。

  • 1) Thin Ni ENEPIG

    - Bonding Pad的 Ni 厚度减小，改善 RF 特性

    Thin Ni ENEPIG
    • Gold, Nickel, Copper, Palladium
    • Ni 厚度: 5~6.5um ENIG/ENEPIG
    • Gold, Nickel, Palladium, Copper
    • Ni 厚度: 0.1um Thin Ni ENEPIG
    * ENIG : Electroless Nickel Immersion Gold
    * ENEPIG : Electroless Nickel Electroless Palladium Immersion Gold

  • 2) Selective ENEPIG

    - 可在同一面进行两种表面处理(ENEPIG + OSP)

    Selective ENEPIG
    • Lorem Ipsum, ENEPIG, OSP
    • ENEPIG + OSP
    * OSP : Organic Solderability Preservative

Lineup

Lineup by Specification
Mass Production Sample Available
Lineup by Specification Layer Structure, Cored etc.
Layer Structure Cored 4L / 6L / 8L 4L / 6L / 8L
Coreless 5L / 7L 6L / 8L / 9L
Line Width / Space 25 / 25 um 20 / 30 um
Bump Pitch 150 um 130 um
Cu Thickness 15 um 15 um
Surface Finish Direct Au, Thin ENEPIG Selective ENEPIG Direct Au, Thin ENEPIG Selective ENEPIG

FCBGA(Flip Chip Ball Grid Array)

将半导体芯片和主板硬性连接的集成封装基板。通过Flip Chip Bump连接半导体芯片和封装基板，提升电、热特性的集成封装基板。而且随着CPU基板电路的集成化，要求基板层数增加， 层间细微整合，同时还要求具备能够实现系列薄型化的薄型基板生产能力。

应用
PC, Server, TV, Set Top Box, Automotive, Game Console
Lineup FCBGA 2017~2020 PC(CPU), Automotive etc.
  ’17年 ’18年 ’19年 ’20年
PC(CPU) Fab : 14nm 14 10 7
Automotive(Infotainment)(AVN) Fab : 28nm 14 10 7
FCBGA 层数 10层(4-2-4) 10层(4-2-4) 10层(4-2-4) 10层(4-2-4)
整合(Land to Pad) 14um 14um 14um 12.5um
电路(Line/Space) 8/8um 8/8um 8/8um 8/8um
* 从CPU 14㎚ : 8层, 14.5um LtP到 CPU 10㎚ : 10层, 14um LtP，基板生产难度增加。

Lineup

FCB有 Standard Core、Thin Core产品。
Mass Production Sample Available
Lineup FCB FCB有 Standard Core、Thin Core产品。
Core Thickness (um) Line Width/Space
Bump Pitch
(Mass Volume)		  
4L 6L 8L 10L 12L 14L 16L
Standard Core 800 9 / 12 um
130 um		              
700              
400              
Thin Core 250 13 / 14 um
130 um		              
200              
100              

*um stands for ㎛

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