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Package Substrate

High-Density Circuit Substrate

The product is a package substrate that is used for the core semiconductors of mobile devices and PCs. It transmits electric signals between semiconductors and the main board, and protects expensive semiconductors from external stress. Compared with general substrates, as this substrate is a high-density circuit substrate containing more microcircuits, the assembly defects and incurred costs in directly bonding expensive semiconductors to the substrate can be reduced.

FCCSP(Flip Chip Chip Scale Package)

This is called Flip Chip Chip Scale Package (FCCSP) as semiconductor chips are upturned and connected to a board through a bump rather than wire bonding. It is mainly used for the application processor (AP) chips of mobile IT devices. Also Compared to WBCSP using Gold Wire, the process using Flip Chip can be applied to high-density semiconductors because the route of electrical signals is shorter, and larger input and output can be accommodated.

Mobile Application Processor, Baseband and Others
Semiconductor Chip -> Bumping(Solder) -> Flip -> Packaging(PCB)

Key Core Technologies

1. Bumping Structure
Bumping Structure image
2. μBall Bump Method
μBall Bump Method image
[Conventional Method]
Solder Paste -> Squeegee -> Metal mask
[Micro Ball Method]
MetalMask -> SolderBall
  • · Available for Fine Bump Pitch
  • · Good for Small Bump Risk
  • · Good Quality for Bump Characteristics

Substrate Type

1. EPS(Embedded Passive Substrate) & EDS(Embedded Die Substrate)

EPS/EDS is a substrate that can be mass-produced by embedding semiconductor passive elements and the IC, among other components, inside the board.
Decoupling capacitors are typically used to stabilize power supply voltage levels.
By embedding the IC inside the board, package size and thickness can be reduced.

2. ETS(Embedded Trace Substrate)

ETS is a circuit board whose circuit pattern is in the insulating material. ETS has a coreless structure, which allows for the implementation of microcircuits without the need for additional cost. Layer Down is performed much easier (4L → 3L). Also As the etching process is not affected by the pattern width, the circuit width can be precisely controlled.

[2Layer Buried Trace], [3Layer Buried Trace], [4Layer Buried Trace]


Lineup by Specification
Mass Production Sample Available
Lineup by Specification Routing Density, Build-Up Line Width / Space etc.
Routing Density Build-Up Line Width / Space 8 / 10um 7 / 9um
BVH / Pad Registration 50 / 80um 45 / 75um
SRO Diameter SR Registration 55 ± 8um 50 ± 8um
FC Bump Pitch (Peripheral) 35um 30um
FC Bump Pitch (Area) 125um 125um
Low Z-Height Core / PPG Thickness 40 / 18um 35 / 15um
SR Thickness 8 ± 3um 7 ± 2um

WBCSP(Wire Bonding Chip Scale Package)

This is a semiconductor chip the size of which is more than 80% of that of the finished part. It is called WBCSP (Wire Bonding CSP) because a gold wire bonding method is applied to connect the semiconductor chip and the PCB. A gold wire is used to connect the chip and PCB, and multi-packaging is possible, which makes the product mainly applicable for memory chips. In particular, UTCSP (Ultra Thin CSP) products are made with a thickness of 0.13mm or thinner. With a high degree of freedom in the chip to PCB connection, multi-chip packaging is made possible, and better performance is realized compared with other products of the same thickness.

Mobile Equipment Memory
  • 1. Mold
  • 2. Tape Substrate
  • 3. Gold Wire
  • 4. Solder Ball
  • 5. Copper Trace
  • [View of Gold Wire Connected]


Lineup by Specification
General WBCSP Road Map of HVM / Sample Product Mass Production Sample Available
Lineup by Specification Routing Density, Bond Finger Pitch etc.
Routing Density Bond Finger Pitch 65P (37 / 15, Ni 2) 60P (32 / 15, Ni 2)
Line Width / Space 50 Pitch 40 Pitch
SRO Diameter Tolerance ± 15um ± 10um
Ball SR Registration
(After Compensation)
± 17.5um ± 16um
Low Z-Height Core/PPG
2Layer 80um 80um
3Layer 80um 80um
4Layer 120um 120um
Lineup by Structure
Mass Production Sample Available
Lineup by Structure Core, Layer, Pattern etc.
Core Layer Count Pattern Structure
Cored 2Layer Normal
Cored 4Layer Normal
Coreless 3Layer Normal
Coreless 4Layer Normal

SiP(System in Package)

This product is developed by realizing complex functions into one system by mounting multiple ICs and passive components in a package. It is also used in products such as Power Amplifiers (PA) and has heat dissipation characteristics. The product series include Flip-Cip SiP and Coreless.

PA(Power Amplifier), PAMID (Power Amplifier Module with Integrated Duplexer), FEMID(Front-End Module with Integrated Duplexer),
SAW Filter, BAW Filter, Various RF Parts like Diversity FEM and Switch


1. Miniaturization

Can realize small packages as multiple ICs and passive components are integrated into one module.

[SiP Composition Shape]
  • 1. Sip
  • 2. Die 1
  • 3. Die 2
  • 4. Die 3
2. Thin Substrate

Can realize 0.2mm thin substrate (based on a 6-layer substrate) by securing the driving capability of ultrathin sheets.

[ 0.2T 6L RF-SiP ](200um), [ 0.27T 8L RF-SiP ](270um), [ 10L ~, 5G Antenna Module ]

Key Core Technologies

1. Coreless RF-SiP

Signal characteristics can be enhanced by controlling Electromagnetic Interference (EMI) and the parasitic inductance by lowering the insulation thickness through the application of the coreless method. This serves as the basis for materializing thin substrates.

Cored Substrate, Coreless Substrate *Thin substrate Can realize
2. ENEPIG Surface Treatment

The ENEPIG surface treatment technology has the following characteristics.

  • 1) Thin Ni ENEPIG

    - RF performance is possible based on the Ni thickness.

    Thin Ni ENEPIG
    • Gold, Nickel, Copper, Palladium
    • Ni Thickness: 5~6.5um ENIG/ENEPIG
    • Gold, Nickel, Palladium, Copper
    • Ni Thickness: 0.1um Thin Ni ENEPIG
    * ENIG : Electroless Nickel Immersion Gold
    * ENEPIG : Electroless Nickel Electroless Palladium Immersion Gold
  • 2) Selective ENEPIG

    - Selective ENEPIG allows the treatment of different surface types
    on the same board. (ENEPIG + OSP)

    Selective ENEPIG
    • Lorem Ipsum, ENEPIG, OSP
    • ENEPIG + OSP
    * OSP : Organic Solderability Preservative


Lineup by Specification
Mass Production Sample Available
Lineup by Specification Layer Structure, Cored etc.
Layer Structure Cored 4L / 6L / 8L 4L / 6L / 8L
Coreless 5L / 7L 6L / 8L / 9L
Line Width / Space 25 / 25 um 20 / 30 um
Bump Pitch 150 um 130 um
Cu Thickness 15 um 15 um
Surface Finish Direct Au, Thin ENEPIG Selective ENEPIG Direct Au, Thin ENEPIG Selective ENEPIG

FCBGA(Flip Chip Ball Grid Array)

The product is a high-integration package substrate that is used to connect a high-integration semiconductor chip to a main board. It is a highly-integrated package board that improves electrical and thermal characteristics by connecting the semiconductor chip and package board with Flip Chip Bump. In addition, the high integration of the CPU board circuitry requires an increase in the number of board layers and fine matching between layers; at the same time, the ability to manufacture thin boards for slimming sets is required.

PC, Server, TV, Set Top Box, Automotive, Game Console
Lineup FCBGA 2017~2020 PC(CPU), Automotive etc.
  2017 2018 2019 2020
PC(CPU) Fab : 14nm 14 10 7
Automotive(Infotainment)(AVN) Fab : 28nm 14 10 7
FCBGA Layer No 10Layer(4-2-4) 10Layer(4-2-4) 10Layer(4-2-4) 10Layer(4-2-4)
Land to Pad 14um 14um 14um 12.5um
Line/Space 8/8um 8/8um 8/8um 8/8um
* Increased board manufacturing difficulty from CPU 14nm: 8 layers, 14.5um LtP to CPU 10nm: 10 layers, 14um LtP


FCB is available in Standard Core, Thin Core type products.
Mass Production Sample Available
Lineup FCB Core Thickness, Line Width/Space Bump Pitch(Mass Volume) etc.
Core Thickness (um) Line Width/Space
Bump Pitch
(Mass Volume)
4L 6L 8L 10L 12L 14L 16L
Standard Core 800 9 / 12 um
130 um
Thin Core 250 13 / 14 um
130 um

*um stands for ㎛

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